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The XS1-L1〔(【引用サイトリンク】title=XCore XS1-L1 datasheet )〕 is a 32-bit processor designed by XMOS, featuring support for up to 8 concurrent threads. It was available as of June 2009 running at 400 MHz. As of April 2010 500 MHz versions are available. Each thread can run at up to 125 MHz; four threads follow each other through the pipeline, resulting in a top speed of 500 MIPS if at least four threads are active. The 500 MIPS of each core is equally distributed over all active threads. This allows the use of extra threads in order to hide latency. == Description == An XS1-L node comprises a single core processor and a switch. The execution core has a data path, a memory, and register banks for eight threads. The switches of two or more XS1-L nodes can be connected using a link, whereupon threads on all of the cores can communicate with each other by exchanging messages through the switches. The switching mechanism is abstracted by means of a channel, a virtual connection between two threads. The switch has eight external links, permitting a maximum throughput of 3.2 GBits/s to other cores. An XS1-L1 device comprises a single XS1-L node; an XS1-L2 device comprises two XS1-L nodes connected by means of 4 links.〔〔(【引用サイトリンク】title=XCore XS1-L2 datasheet )〕 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「XCore XS1-L1」の詳細全文を読む スポンサード リンク
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